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authorBoris Brezillon <boris.brezillon@free-electrons.com>2016-03-04 17:21:35 +0100
committerBoris Brezillon <boris.brezillon@free-electrons.com>2016-04-19 22:05:40 +0200
commitece03cfd5260e0349442dea1d1065f44fbed1ea8 (patch)
treea91eb933f8a30326c1ae3b16036ff92908acd549
parente9aa671f69acb87db4835e4f0b41f5fa16d16562 (diff)
mtd: nand: sunxi: let the NAND controller control the CE line
We don't need to manually toggle the CE line since the controller handles it for us. Moreover, keeping the CE line low when interacting with a DDR NAND can be problematic (data loss in some corner cases). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-rw-r--r--drivers/mtd/nand/sunxi_nand.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index ab572dd..4dcc0e4 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -514,21 +514,11 @@ static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
int ret;
- u32 tmp;
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
if (ret)
return;
- if (ctrl & NAND_CTRL_CHANGE) {
- tmp = readl(nfc->regs + NFC_REG_CTL);
- if (ctrl & NAND_NCE)
- tmp |= NFC_CE_CTL;
- else
- tmp &= ~NFC_CE_CTL;
- writel(tmp, nfc->regs + NFC_REG_CTL);
- }
-
if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
!(ctrl & (NAND_CLE | NAND_ALE))) {
u32 cmd = 0;