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authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-06-22 11:15:55 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-07-04 21:18:11 +0200
commit73ba3a1c64a4c5a1a4b87c773714814eecb84877 (patch)
treebceada543b22eaf161c181500c1f1eb418489daf
parent6a706356b4456204fd89ef3fbfc6ed4165cebf37 (diff)
ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate
In order to be able to properly generate its pixel clock, the pll3-2x fixed factor needs to be able to change the PLL3 rate too. Add the needed extra compatible so that it behaves that way. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sun5i.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 0840612..e374f4f 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -130,7 +130,7 @@
};
pll3x2: pll3x2_clk {
- compatible = "fixed-factor-clock";
+ compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <2>;