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authorBoris Brezillon <boris.brezillon@free-electrons.com>2015-12-02 15:10:40 +0100
committerBoris Brezillon <boris.brezillon@free-electrons.com>2016-04-19 22:05:37 +0200
commit2f9992e080b8892a10d189cbc846c06e6594ad0b (patch)
tree6c1f9950de031377b53548fde1a413181bc5101f
parent9edb47004e2afb5884d0c900cbd1ece8b2d6f403 (diff)
mtd: nand: sunxi: fix clk rate calculation
Unlike what is specified in the Allwinner datasheets, the NAND clock rate is not equal to 2/T but 1/T. Fix the clock rate selection accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-rw-r--r--drivers/mtd/nand/sunxi_nand.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 546a9ca..05b3303 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1208,12 +1208,12 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
/*
- * Convert min_clk_period into a clk frequency, then get the
- * appropriate rate for the NAND controller IP given this formula
- * (specified in the datasheet):
- * nand clk_rate = 2 * min_clk_rate
+ * Unlike what is stated in Allwinner datasheet, the clk_rate should
+ * be set to (1 / min_clk_period), and not (2 / min_clk_period).
+ * This new formula was verified with a scope and validated by
+ * Allwinner engineers.
*/
- chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
+ chip->clk_rate = NSEC_PER_SEC / min_clk_period;
return 0;
}