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authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-07-11 22:34:47 +0200
committerMichael Turquette <mturquette@baylibre.com>2016-07-11 14:34:54 -0700
commit0bd8fa260821f34a64163c01a74f293745527cef (patch)
treebfc78891ed78dfe70d9720fe1c1795eeabb09e1b
parent0577e4853bfb4c65f620fa56d3157692df7f766e (diff)
clk: sunxi-ng: h3: Fix audio clock divider offset
The code had a typo and got the wrong offset for the hardcoded divider, fix that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reported-by: Jean-Francois Moine <moinejf@free.fr> Reported-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index bcc0a95..9af35954 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
- val &= ~GENMASK(4, 0);
- writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG);
+ val &= ~GENMASK(19, 16);
+ writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
}