diff options
| author | Rob Herring <robh@kernel.org> | 2021-10-06 11:43:31 -0500 |
|---|---|---|
| committer | James Morse <james.morse@arm.com> | 2021-11-12 19:01:18 +0000 |
| commit | 7cfc8ff4c2167d8b7da45a3a5f7f7f98de31bcde (patch) | |
| tree | 084e1cfbacb6f0fbe4743ea994460ba75c539081 | |
| parent | 0f69a55a000f4dd3ac0e8f03b29868c85d6b4545 (diff) | |
| download | linux-7cfc8ff4c2167d8b7da45a3a5f7f7f98de31bcde.tar.gz | |
cacheinfo: Allow for >32-bit cache 'id'
In preparation to set the cache 'id' based on the CPU h/w ids, allow for
64-bit bit 'id' value. The only case that needs this is arm64, so
unsigned long is sufficient.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
[ Update get_cpu_cacheinfo_id() too ]
Signed-off-by: James Morse <james.morse@arm.com>
| -rw-r--r-- | drivers/base/cacheinfo.c | 8 | ||||
| -rw-r--r-- | include/linux/cacheinfo.h | 10 |
2 files changed, 12 insertions, 6 deletions
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index dad2962291614..66d10bdb863b5 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -366,13 +366,19 @@ static ssize_t file_name##_show(struct device *dev, \ return sysfs_emit(buf, "%u\n", this_leaf->object); \ } -show_one(id, id); show_one(level, level); show_one(coherency_line_size, coherency_line_size); show_one(number_of_sets, number_of_sets); show_one(physical_line_partition, physical_line_partition); show_one(ways_of_associativity, ways_of_associativity); +static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct cacheinfo *this_leaf = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%lu\n", this_leaf->id); +} + static ssize_t size_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index a278e58b51a2d..afc9b186c0678 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -48,7 +48,7 @@ extern unsigned int coherency_max_size; * keeping, the remaining members form the core properties of the cache */ struct cacheinfo { - unsigned int id; + unsigned long id; enum cache_type type; unsigned int level; unsigned int coherency_line_size; @@ -106,23 +106,23 @@ const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf); * Get the id of the cache associated with @cpu at level @level. * cpuhp lock must be held. */ -static inline int get_cpu_cacheinfo_id(int cpu, int level) +static inline unsigned long get_cpu_cacheinfo_id(int cpu, int level) { struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu); int i; if (!ci->info_list) - return -1; + return ~0ULL; for (i = 0; i < ci->num_leaves; i++) { if (ci->info_list[i].level == level) { if (ci->info_list[i].attributes & CACHE_ID) return ci->info_list[i].id; - return -1; + return ~0ULL; } } - return -1; + return ~0ULL; } /* |